VERILOG PROGRAMS

1.Adder/Subtractor

1 (a) : 4 – bit BINARY ADDER

Code

 1 (b) : 4 – bit BINARY SUBTRACTOR

Code

4 – bit BINARY ADDER Code

 module BinaryAdder4bit_STRUCT(Sum,Cout,A,B,Cin);

output [3:0] Sum;

output Cout;

input [3:0] A,B;

input Cin;

 

FullAdder_STRUCT FA0 (Sum[0],W1,A[0],B[0],Cin);

FullAdder_STRUCT FA1 (Sum[1],W2,A[1],B[1],W1);

FullAdder_STRUCT FA2 (Sum[2],W3,A[2],B[2],W2);

FullAdder_STRUCT FA3 (Sum[3],Cout,A[3],B[3],W3);

 endmodule

module FullAdder_STRUCT(Sum,Cout,A,B,Cin);

output Sum,Cout;input A,B,Cin;

assign Sum=A^B^Cin;

assign Cout=((A&B)|(B&Cin)|(A&Cin));

endmodule

 Test bench

`timescale 1ns / 1ps

 module tb_BinaryAdder4bit_STRUCT;

 reg [3:0] A,B;

reg Cin;

wire [3:0] Sum;

wire Cout;

 BinaryAdder4bit_STRUCT uut (Sum,Cout,A,B,Cin);

initial  begin

            A=2;

            B=5;

            Cin=1;

    #20 {A,B,Cin}={4’d7,4’d7,1’b1};

    #20 {A,B,Cin}={4’d15,4’d15,1’b0};

    #20 {A,B,Cin}={4’d15,4’d15,1’b1};

    #20 $finish;

  end    

endmodule

***************************************************************************

1 (b) : 4 – bit BINARY SUBTRACTOR Code

`timescale 1ns / 1ps

module BinarySubtractor4bit_STRUCT(Diff,Bout,A,B,Bin);

output [3:0] Diff;

output Bout;

input [3:0] A,B;

input Bin;            

FullSubtractor_STRUCT FS0 (Diff[0],W1,A[0],B[0],Bin);

FullSubtractor_STRUCT FS1 (Diff[1],W2,A[1],B[1],W1);

FullSubtractor_STRUCT FS2 (Diff[2],W3,A[2],B[2],W2);

FullSubtractor_STRUCT FS3 (Diff[3],Bout,A[3],B[3],W3);            

endmodule

module FullSubtractor_STRUCT(Diff,Boro,A,B,Bin);  

output Diff,Boro; input A,B,Bin;

assign Diff=A^B^Bin;

assign Boro=(((~A)&B)|(B&Bin)|((~A)&Bin));

endmodule            

Test bench

 `timescale 1ns / 1ps

 module tb_BinarySubtractor4bit_STRUCT;

reg [3:0] A,B;

reg Bin;

wire [3:0] Diff;

wire Bout;

BinarySubtractor4bit_STRUCT uut (Diff,Bout,A,B,Bin);

 initial  begin

            A=0;    B=0;   Bin=0;

    #20 {A,B,Bin}={4’d5,4’d2,1’b0};

    #20 {A,B,Bin}={4’d15,4’d8,1’b1};

    #20 {A,B,Bin}={4’d5,4’d6,1’b0};

    #20 $finish;

  end    

endmodule

*****************************************************************************************

2 (a) : 2x1 MULTIPLEXER in GATE LEVEL

`timescale 1ns / 1ps

module Mux2x1_GL(Out,S,In0,In1);

output Out;

input S,In0,In1;

not (Sbar,S);

and (W1,In0,Sbar);

and (W2,In1,S);

or  (Out,W1,W2);

endmodule

 Test bench

`timescale 1ns / 1ps

module tb_Mux2x1_GL;

reg S,In0,In1;

wire Out;

Mux2x1_GL uut (Out,S,In0,In1);

 initial

  begin

            S = 0;

            In0 = 0;

            In1 = 0;

    #50 S=1;

    #50 S=0;

    #50 $finish;

   end            

always

     #2 In0=~In0;          

always

     #5 In1=~In1;             

endmodule

*************************************************************

2 (b) : 2x1 MULTIPLEXER in DATAFLOW

Code

`timescale 1ns / 1ps

module Mux2x1_DF(Out,S,In0,In1);

output Out;

input S,In0,In1;

assign Sbar=~S;

assign Out=(Sbar&In0) | (S&In1);

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Mux2x1_DF;

reg S,In0,In1;

wire Out;

// Instantiate the Unit Under Test (UUT)

Mux2x1_DF uut (Out,S,In0,In1);

initial

  begin

            S = 0;

            In0 = 0;

            In1 = 0;

    #50 S=1;

    #50 S=0;

    #50 $finish;

   end

            

always

     #2 In0=~In0;

          

always

     #5 In1=~In1;

             

endmodule

*******************************************************************************

2 (c) : 2x1 MULTIPLEXER using IF-ELSE

Code

`timescale 1ns / 1ps

module Mux2x1_If(output reg Out,input S,input In0,input In1);

always @ (S,In0,In1)

  begin

    if (S==0)

               Out=In0;

             else

               Out=In1;

  end

endmodule

 Test bench

`timescale 1ns / 1ps

module tb_Mux2x1_If;

reg S,In0,In1;

wire Out;

// Instantiate the Unit Under Test (UUT)

Mux2x1_If  uut (Out,S,In0,In1);

initial

  begin

            S = 0;

            In0 = 0;

            In1 = 0;

    #50 S=1;

    #50 S=0;

    #50 $finish;

   end

            

always     #2 In0=~In0;

          

always     #5 In1=~In1;

endmodule

********************************************************************************

2 (d) : 4x1 MULTIPLEXER using 2x1 MULTIPLEXERS

Code

`timescale 1ns / 1ps

module Mux4x1_Struct(Out,S,In0,In1,In2,In3);

output Out;

input [1:0] S;

input In0,In1,In2,In3;

Mux2x1_GL M10 (W1,S[0],In0,In1);

Mux2x1_GL M11 (W2,S[0],In2,In3);

Mux2x1_GL M21 (Out,S[1],W1,W2);

endmodule

Test bench

`timescale 1ns / 1ps

module tb_Mux4x1_Struct;

reg In0,In1,In2,In3;

reg [1:0] S;

wire Out;

Mux4x1_Struct uut (Out,S,In0,In1,In2,In3);

initial

  begin

          S = 0;

       In0 = 0;

       In1 = 0;

       In2 = 0;

       In3 = 1;

    #40 S=1;

    #40 S=2;

    #40 S=3;

    #40 $finish;

  end

always  #2 In0=~In0;

always  #6 In2=~In2;

          

                

endmodule

*******************************************************************

3 (a) : 8x3 ENCODER with ENABLE

Code

module Enc8x3(Y,En,A);

output reg [2:0] Y;

input En;

input [7:0] A;

always @ (En,A)

  begin

    if (En==1)

      begin

        case(A)

            8’b0000_0001 : Y=3’b000;

            8’b0000_0010 : Y=3’b001;

            8’b0000_0100 : Y=3’b010;

            8’b0000_1000 : Y=3’b011;

            8’b0001_0000 : Y=3’b100;

            8’b0010_0000 : Y=3’b101;

            8’b0100_0000 : Y=3’b110;

            8’b1000_0000 : Y=3’b111;

                   default      : Y=3’b000;

       endcase

      end

    else Y=3’bz;

 end

endmodule

Test bench

module tb_Enc8x3;

reg En;

reg [7:0] A;

wire [2:0] Y;

Enc8x3 uut (Y,En,A);

initial begin

          En = 1;A = 0;

   #20 A=1;  #20 A=2;  #20 A=4;  #20 A=8;  #20 A=16;  #20 A=32;

   #20 A=64;#20 A=8’bx11;  #20 En=0;  #20 A=4;  #20 A=8;  #20 A=16;

   #20 $finish;

  end

endmodule

***************************************************************************

3 (b) : 3X8 DECODER with ENABLE

Code

module Dec3x8(Y,En,A);

output reg [7:0] Y;

input En;

input [2:0] A;

always @ (En,A)

  begin

    if (En==1)

      begin

        case(A)

            3’b000 : Y=8’b0000_0001;

            3’b001 : Y=8’b0000_0010;

            3’b010 : Y=8’b0000_0100;

            3’b011 : Y=8’b0000_1000;

            3’b100 : Y=8’b0001_0000;

            3’b101 : Y=8’b0010_0000;

            3’b110 : Y=8’b0100_0000;

            3’b111 : Y=8’b1000_0000;

            default : Y=8’b0000_0000;

        endcase

      end

   else Y=8’bz;

  end

endmodule

            

Test bench

`timescale 1ns / 1ps

module tb_Dec3x8;

reg En;

reg [2:0] A;

wire [7:0] Y;

Dec3x8 uut (Y,En,A);

initial begin

           En = 1;A = 0;

   #20 A=1;  #20 A=2;  #20 A=3;  #20 A=4;  #20 A=5;  #20 A=6;

   #20 A=7; #20 A=3’b11x;  #20 En=0;  #20 A=4;  #20 A=5;  #20 A=6;

   #20 $finish;

end

endmodule

**************************************************************************************************

3 (c) : 4x2 PRIORITY ENCODER with ENABLE

Code

module PriorityEnc4x2(Y,En,A);

output reg [1:0] Y;

input En;

input [3:0] A;

always @ (A,En)

  begin

     if (En==1)

       begin

         casex(A)

4’bxxx1 : Y=2’b00;

4’bxx1x : Y=2’b01;

4’bx1xx : Y=2’b10;

4’b1xxx : Y=2’b11;

 default : Y=2’bx;

        endcase

      end

   else Y=2’bz;

 end

endmodule

Test bench

module tb_PriorityEnc4x2;

reg En;

reg [3:0] A;

wire [1:0] Y;

PriorityEnc4x2 uut (Y,En,A);

initial begin

          En = 1;A = 0;

  #20 A=4’b1100;

  #20 A=4’b0111;

  #20 A=4’b11x0;

  #20 A=4’b0011;

  #20 $finish; 

end

endmodule

***************************************************************************

3 (d) : 4 – bit COMPARATOR

Code

module Comp4bit(AgtB,AeqB,AltB,A,B);

output reg AgtB,AeqB,AltB;

input [3:0] A,B;

always @ (A,B)

  begin

       AgtB=0;AeqB=0;AltB=0;

    if (A>B)

        AgtB=1;

    else if (A==B)

        AeqB=1;

    else if (A<B)

        AltB=1;

    else

      begin

        AgtB=1’bx;

        AeqB=1’bx;

        AltB=1’bx;

    end

  end

endmodule

            

Test bench

module tb_Comp4bit;

reg [3:0] A,B;

wire AgtB,AeqB,AltB;

Comp4bit uut (AgtB,AeqB,AltB,A,B);

initial begin

         A = 0;B = 0;

  #20 A=5; B=7;

  #20 A=7;

  #20 A=10;

  #20 B=4’b111x;

  #20 $finish;

end

endmodule

*********************************************************************************

4 (a) : 8 – bit PARALLEL ADDER using 4 – bit task

Code

`timescale 1ns / 1ps

module CLAAdder_task(Sum,Cout,A,B,Cin);

output reg [7:0] Sum;

output reg Cout;

input [7:0] A,B;

input Cin;

reg w1;

always @ (A or B or Cin)

begin

CLAAdder_4bit (Sum[3:0],w1,A[3:0],B[3:0],Cin);

CLAAdder_4bit (Sum[7:4],Cout,A[7:4],B[7:4],w1);

end

 task automatic CLAAdder_4bit;

output [3:0] sum;

output cout;

input [3:0] a,b;

input cin;

reg [3:0] c,g,p;

begin

c[0]=cin;

sum[0]=a[0]^b[0]^c[0];

g[0]=a[0]&b[0];

p[0]=a[0]|b[0];

c[1]=g[0] | (p[0]&c[0]);

sum[1]=a[1]^b[1]^c[1];

g[1]=a[1]&b[1];

p[1]=a[1]|b[1];

c[2]=g[1] | (p[1]&g[0]) | (p[1] & p[0] & c[0]);

sum[2]=a[2]^b[2]^c[2];

g[2]=a[2]&b[2];

p[2]=a[2]|b[2];

c[3]=g[2] | (p[2]&g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c[0]);

sum[3]=a[3]^b[3]^c[3];

g[3]=a[3]&b[3];

p[3]=a[3]|b[3];

cout=g[3] | (p[3]&g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & c[0]);

end

endtask

endmodule

***************************************************************

4 (b) : 8 – bit PARALLEL ADDER using 4 – bit function

Code

`timescale 1ns / 1ps

module CLAAdder_func(Sum,Cout,A,B,Cin);

output reg [7:0] Sum;

output reg Cout;

input [7:0] A,B;

input Cin;reg w1;

always @ (A or B or Cin)

begin

{w1,Sum[3:0]} = CLAAdder_4bit(A[3:0],B[3:0],Cin);

{Cout,Sum[7:4]} = CLAAdder_4bit(A[7:4],B[7:4],w1);

end

function automatic [4:0] CLAAdder_4bit;

input [3:0] a,b;

input cin;

reg [3:0] sum;

reg cout;

reg [3:0] c,g,p;

begin

c[0]=cin;

sum[0]=a[0]^b[0]^c[0];

g[0]=a[0]&b[0];

p[0]=a[0]|b[0];

c[1]=g[0] | (p[0]&c[0]);

sum[1]=a[1]^b[1]^c[1];

g[1]=a[1]&b[1];

p[1]=a[1]|b[1];

c[2]=g[1] | (p[1]&g[0]) | (p[1] & p[0] & c[0]);

sum[2]=a[2]^b[2]^c[2];

g[2]=a[2]&b[2];

p[2]=a[2]|b[2];

c[3]=g[2] | (p[2]&g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & c[0]);

sum[3]=a[3]^b[3]^c[3];

g[3]=a[3]&b[3];

p[3]=a[3]|b[3];

cout=g[3] | (p[3]&g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & c[0]);

CLAAdder_4bit={cout,sum[3:0]};

end

endfunction

endmodule

********************************************************************************

5.ALU with 8 INSTRUCTIONS

Code

`timescale 1ns / 1ps

module ALU(Y,S,A,B);

output reg [7:0] Y;

input [2:0] S;

input [3:0] A,B;

always @ (A or B or S)

  begin

    case(S)

        3’b000 : Y=A+B;

        3’b001 : Y=A-B;

        3’b010 : Y=B-A;

        3’b011 : Y=A*B;

        3’b100 : Y=A&B;

        3’b101 : Y=A|B;

        3’b110 : Y=A;

        3’b111 : Y=B;

       default : Y=8’bx;

  endcase

 end

endmodule

            

Test bench

`timescale 1ns / 1ps

module tb_ALU;

reg [2:0] S;

reg [3:0] A,B;

wire [7:0] Y;

 ALU uut (Y,S,A,B);

initial begin

           S = 0;A = 4;B = 2;

    #20 S=1;

    #20 S=2;

    #20 S=3;

    #20 S=4;

    #20 S=5;

    #20 S=6;

    #20 S=7;

    #20 $finish;

 end

 endmodule

*************************************************************

6 (a). SR - FLIP-FLOP

Code

module SRFF(Q,S,R,Clk,Rst);

output reg Q;

input S,R,Clk,Rst;

always @ (posedge Clk or posedge Rst)

  begin

    if (Rst==1’b1)

       Q<=1’b0;

    else

       case({S,R})

            2’b00 : ;

            2’b01 : Q<=1’b0;

            2’b10 : Q<=1’b1;

            2’b11 : Q<=1’bx;

      endcase

 end

endmodule

Test bench

module tb_SRFF;

reg S,R,Clk,Rst;

wire Q;

SRFF uut (Q,S,R,Clk,Rst);

initial

  begin

         S= 0;R = 0;Clk = 0;Rst = 0;

    #5 Rst=1;

    #30 Rst=0;

    #22 S=1;R=0;

    #22 S=0;R=1;

    #22 S=1;R=1;

    #50 $finish;

  end

always #5 Clk=~Clk;    

endmodule

***********************************************************

6 (b). JK - FLIP-FLOP

Code

module JKFF(Q,J,K,Clk,Rst);

output reg Q;

input J,K,Clk,Rst;

always @ (posedge Clk or posedge Rst)

  begin

     if (Rst==1’b1)

       Q<=1’b0;

    else

       case({J,K})

            2’b00 : ;

            2’b01 : Q<=1’b0;

            2’b10 : Q<=1’b1;

            2’b11 : Q<=~Q;

       endcase

  end

endmodule

Test bench

module tb_JKFF;

reg J,K,Clk,Rst;

wire Q;

JKFF uut (Q,J,K,Clk,Rst);

initial

  begin

          J= 0;K = 0;Clk = 0;Rst = 0;

    #5 Rst=1;

    #30 Rst=0;

    #22 J=1;K=0;

    #22 J=0;K=1;

    #22 J=1;K=1;

    #50 $finish;

  end

always #5 Clk=~Clk;

endmodule

************************************************************

6 (c) : D - FLIP-FLOP

Code

module DFF(Q,D,Clk,Rst);

output reg Q;

input D,Clk,Rst;

always @ (posedge Clk or posedge Rst)

  begin

    if (Rst==1’b1)

       Q<=1’b0;

    else

      Q<=D;

   end

endmodule

Test bench

module tb_DFF;

reg D,Clk,Rst;

wire Q;

DFF uut (Q,D,Clk,Rst);

initial

 begin

           D = 0;

          Clk = 0;

          Rst = 0;

   #50 Rst=1;

   #30 Rst=0;

  #20 $finish;

end

always #10 Clk=~Clk;          

always #3 D=~D;          

endmodule

**********************************************************************

6 (d) : T - FLIP-FLOP

Code

module TFF(Q,T,Clk,Rst);

output reg Q;

input T,Clk,Rst;

always @ (posedge Clk or posedge Rst)

  begin

    if (Rst==1’b1)

      Q<=1’b0;

   else

      Q<=Q^T;

   end

endmodule

Test bench

module tb_TFF;

reg T,Clk,reg Rst;

wire Q;

TFF uut (Q,T,Clk,Rst );

initial

 begin

          T = 0;

          Clk = 0;

          Rst = 0;

          T=1;

   #50 Rst=1;

   #30 Rst=0;

   #70 T=0;

   #50 $finish;

 end 

always #5 Clk=~Clk;          

endmodule

 ******************************************************************

7 (a) : UNIVERSAL SHIFT REGISTER

Code

`timescale 1ns / 1ps

module UniversalShiftRegister(RegOut,S,RegIn,Clk,Rst);

output reg [7:0] RegOut;

input [2:0] S;

input [7:0] RegIn;

input Clk,Rst;

always @ (posedge Clk or posedge Rst)

if (Rst)

  RegOut <= 8’d0;

else

  case (S)

    3’b000 : RegOut <= RegIn;

             3’b001 : RegOut <= RegOut >> 1;

             3’b010 : RegOut <= RegOut >> 2;

             3’b011 : RegOut <= RegOut << 1;

             3’b100 : RegOut <= RegOut << 2;

             3’b101 : RegOut <= RegOut >>> 1;

             3’b110 : RegOut <= RegOut <<< 1;

             3’b111 : RegOut <= RegOut >> 1;

endcase

endmodule

Test bench

module tb_UniversalShiftRegister;

reg [2:0] S;

reg [7:0] RegIn;

reg Clk,Rst;

wire [7:0] RegOut;

UniversalShiftRegister uut (RegOut,S,RegIn,Clk,Rst);

initial begin

          S = 0;RegIn = 8’d255;Clk = 0;Rst = 0;

  #30 Rst=1;  #30 Rst=0;  #30 S=1;  #15 S=2;  #15 S=3;

  #15 S=4;  #15 S=5;  #15 S=6;  #15 S=7;

  #15 $finish;

end

always #5 Clk=~Clk;

endmodule

*********************************************************************

7 (b) : 4 – bit BINARY UP/DOWN COUNTER with SYNCHRONOUS CLOCK

Code

module BinayUpDownCounter4bit_SyncClk(Count,UpDown,En,Clk,Rst);

output reg [3:0] Count;

input UpDown,En,Clk,Rst;

always @ (posedge Clk or posedge Rst)

begin

  if (Rst==1’b1)

    Count <= 4’b0000;

  else if (En && UpDown)

    Count <= Count + 1’b1;

else if (En && !UpDown)

    Count <= Count - 1’b1;

end

endmodule

Test bench

module tb_BinaryUpDownCounter4bit_SyncClk;

reg UpDown,En,Clk,Rst;

wire [3:0] Count;

BinayUpDownCounter4bit_SyncClk uut (Count,UpDown,En,Clk,Rst);

initial begin

            UpDown = 1;

            En = 1;

            Clk = 0;

            Rst = 0;

    #30 Rst=1;

    #40 Rst=0;

    #170 UpDown=0;

    #200 $finish;

end          

always  #5 Clk=~Clk;    

endmodule

*************************************************************************

7 (c) : BCD UP/DOWN COUNTER with SYNCHRONOUS CLOCK

Code

module BCDUpDownCounter4bit_SyncClk(Count,UpDown,En,Clk,Rst);

output reg [3:0] Count;

input UpDown,En,Clk,Rst;

always @ (posedge Clk or posedge Rst)

begin

  if (Rst==1’b1)

    Count <= 4’b0000;

  else if (En && UpDown)

    begin

    Count <= Count + 1’b1;

               if (Count == 4’b1001)

                   Count <= 4’b0000;

             end

else if (En && !UpDown)

    begin

    Count <= Count - 1’b1;

               if (Count == 4’b0000)

                   Count <= 4’b1001;

             end

end

endmodule

Test bench

module tb_BCDUpDownCounter4bit_SyncClk;

reg UpDown,En,Clk,Rst;

wire [3:0] Count;

BCDUpDownCounter4bit_SyncClk uut (Count,UpDown,En,Clk,Rst);

initial begin

          UpDown = 1;En = 1;Clk = 0;Rst = 0;

   #30 Rst=1;  #40 Rst=0;  #170 UpDown=0;

   #200 $finish;

end

always   #5 Clk=~Clk;

endmodule

**********************************************************************************

7 (d) : 4 – bit BINARY UP/DOWN COUNTER with ASYNCHRONOUS CLOCK

Code

module BinaryUpDownCounter4bit_asyncClk(Count,UpDown,Clk,Rst);

output [3:0] Count;

input UpDown,Clk,Rst;

assign Clk0=Clk;

Mux2x1_GL M0 (Clk1,UpDown,Count[0],~Count[0]);

Mux2x1_GL M1 (Clk2,UpDown,Count[1],~Count[1]);

Mux2x1_GL M2 (Clk3,UpDown,Count[2],~Count[2]);

TFF TFF0 (Count[0],1’b1,Clk0,Rst);

TFF TFF1 (Count[1],1’b1,Clk1,Rst);

TFF TFF2 (Count[2],1’b1,Clk2,Rst);

TFF TFF3 (Count[3],1’b1,Clk3,Rst);

endmodule

Test bench

module tb_BinaryUpDownCounter4bit_asyncClk;

reg UpDown,Clk,Rst;

wire [3:0] Count;

 BinaryUpDownCounter4bit_asyncClk uut (Count,UpDown,Clk,Rst);

initial begin

           Clk = 0;Rst = 0;

    #30 Rst=1;

    #30 Rst=0;UpDown=1;

    #200 UpDown=0;

    #300 $finish;                      

end

always #5 Clk=~Clk;          

endmodule

*******************************************************************

8 (a) : “111” SEQUENCE DETECTOR (Non-Overlapping) using MOORE STATE MACHINE

Code

module SeqDet111NonOverlap_Moore(Y,X,Clk,Rst);

output Y;

input X,Clk,Rst;

parameter State0 = 2’b00;

parameter State1 = 2’b01;

parameter State2 = 2’b10;

parameter State3 = 2’b11;

reg [1:0] Present_state, Next_state;

always @ (posedge Clk or posedge Rst)

begin

 if (Rst==1’b1)  begin

   Present_state <= State0;

   Y <= 1’b0;

   end

 else

   Present_state <= Next_state;

end

always @ (X or Present_state)

begin

  case(Present_state)

             State0 : if (X==1’b1) Next_state <= State1; else if (X==1’b0) Next_state <= State0;

             State1 : if (X==1’b1) Next_state <= State2; else if (X==1’b0) Next_state <= State0;

             State2 : if (X==1’b1) Next_state <= State3; else if (X==1’b0) Next_state <= State0;

             State3 : if (X==1’b1) Next_state <= State1; else if (X==1’b0) Next_state <= State0;

  endcase

end

assign Y = (Next_state == State3);

endmodule

Test bench

module tb_SeqDet111NonOverlap_Moore;

reg X,Clk,Rst;

wire Y;

SeqDet111NonOverlap_Moore uut (Y,X,Clk,Rst);

initial begin

         X = 0;Clk = 0;Rst = 0;

  #30 Rst = 1;  #30 Rst = 0;  #15 X=1;  #75 X=0;  #15 X=1;

  #45 $finish;

end

always #5 Clk=~Clk;

endmodule

************************************************************************

8 (b) : “111” SEQUENCE DETECTOR (Overlapping) using MOORE STATE MACHINE

Code

module SeqDet111Overlap_Moore(Y,X,Clk,Rst);

output Y;

input X,Clk,Rst;

parameter State0 = 2’b00;

parameter State1 = 2’b01;

parameter State2 = 2’b10;

parameter State3 = 2’b11;

reg [1:0] Present_state, Next_state;

always @ (posedge Clk or posedge Rst)

begin

 if (Rst==1’b1)  begin

   Present_state <= State0;

   Y <= 1’b0;

   end

 else

   Present_state <= Next_state;

end

always @ (X or Present_state)

begin

  case(Present_state)

             State0 : if (X==1’b1) Next_state <= State1; else if (X==1’b0) Next_state <= State0;

             State1 : if (X==1’b1) Next_state <= State2; else if (X==1’b0) Next_state <= State0;

             State2 : if (X==1’b1) Next_state <= State3; else if (X==1’b0) Next_state <= State0;

             State3 : if (X==1’b1) Next_state <= State3; else if (X==1’b0) Next_state <= State0;

  endcase

end

assign Y = (Next_state == State3);

endmodule

*****************************************************************************

8 (c) : “111” SEQUENCE DETECTOR (Non-Overlapping) using MEALY STATE MACHINE

Code

module SeqDet111NonOverlap_Mealy(Y,X,Clk,Rst);

output reg Y;

input X,Clk,Rst;

parameter State0 = 2’b00;

parameter State1 = 2’b01;

parameter State2 = 2’b10;

parameter State3 = 2’b11;

reg [1:0] Present_state, Next_state;

always @ (posedge Clk or posedge Rst)

begin

if (Rst==1’b1)  begin

   Present_state <= State0;

   Y <= 1’b0;

   end

 else

   Present_state <= Next_state;

end

always @ (X or Present_state)

begin

  case(Present_state)

    State0 : if (X==1’b1) begin   Next_state <= State1; Y <= 1’b0; end

                 else if (X==1’b0) begin  Next_state <= State0;  Y <= 1’b0;   end

          

    State1 : if (X==1’b1) begin  Next_state <= State2; Y <= 1’b0; end

                 else if (X==1’b0) begin  Next_state <= State0; Y <= 1’b0;  end

    State2 : if (X==1’b1) begin Next_state <= State3; Y <= 1’b1; end

                 else if (X==1’b0) begin Next_state <= State0; Y <= 1’b0;  end

    State3 : if (X==1’b1) begin Next_state <= State1; Y <= 1’b0; end

                 else if (X==1’b0) begin  Next_state <= State0;  Y <= 1’b0;  end                        

  endcase

end

endmodule

******************************************************************************

8 (d) : “111” SEQUENCE DETECTOR (Overlapping) using MEALY STATE MACHINE

Code

module SeqDet111Overlap_Mealy(Y,X,Clk,Rst);

output reg Y;

input X,Clk,Rst;

parameter State0 = 2’b00;

parameter State1 = 2’b01;

parameter State2 = 2’b10;

parameter State3 = 2’b11;

reg [1:0] Present_state, Next_state;

always @ (posedge Clk or posedge Rst)

begin

if (Rst==1’b1)  begin

   Present_state <= State0;

   Y <= 1’b0;

   end

 else

   Present_state <= Next_state;

end

always @ (X or Present_state)

 begin

  case(Present_state)

    State0 : if (X==1’b1) begin Next_state <= State1; Y <= 1’b0; end

                 else if (X==1’b0) begin Next_state <= State0; Y <= 1’b0; end

    State1 : if (X==1’b1) begin Next_state <= State2; Y <= 1’b0; end

                 else if (X==1’b0) begin  Next_state <= State0; Y <= 1’b0; end

    State2 : if (X==1’b1) begin Next_state <= State3; Y <= 1’b1;  end

                 else if (X==1’b0) begin Next_state <= State0; Y <= 1’b0; end

    State3 : if (X==1’b1) begin Next_state <= State3; Y <= 1’b1; end

                 else if (X==1’b0) begin  Next_state <= State0; Y <= 1’b0;   end                        

  endcase

end

endmodule

*******************************************************************